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| Cycle stealing ： ウィキペディア英語版 |
Cycle stealing
Cycle stealing is a method of accessing RAM without interfering with the CPU. It is similar to DMA for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings could permit the CPU to run at full speed without any delay if external devices may sneak in one RAM access to memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict. Such systems are nearly dual-port RAM without the expense of high speed RAM. Most systems halt the CPU during the steal, essentially making it DMA by another name.
For example, a system with separate instruction and data memory banks could allow external devices ONE memory access to the data RAM while the CPU was in op-code-fetch, if both accesses were initiated simultaneously. A MMU is not essential, for the Zilog Z80's M1 line could be used to distinguish instruction from data access, so while the CPU is reading an instruction from instruction-RAM or ROM, the data RAM is available to other devices without disturbing the CPU at all.
==Modern architecture==
Cycle stealing is difficult to achieve in modern systems due to many factors such as pipelining, pre-fetch and concurrent elements constantly accessing memory, leaving few predictable idle times to sneak in memory access. DMA is the only formal and predictable method for external devices to access RAM.
This term is less common in modern computer architecture (say above 66-100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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